In portable communication products such as selective call receivers and cellular telephones, a consumer need for smaller, compact products, has led to a constant challenge among manufacturers to pack more features into smaller packages. In most of these products a printed circuit board (PCB) is used to provide interconnections between devices and components. With the reduction in the size of these communication products, the density of components and devices mounted on a PCB has increased. Consequently, the density of connections on a PCB has increased significantly. Recently, a new method commonly known as direct chip attach (DCA) or flip chip on board (FCOB), has been developed. Using this method, a semiconductor chip is mounted directly to a PCB i.e. the semiconductor chip is flipped over and the bond pads of the semiconductor chip are soldered onto a matching footprint of pads on the PCB. There are several requirements that must be met by a PCB manufacturer when fabricating a PCB for DCA. These requirements include providing a controlled volume of eutectic tin-lead solder on each pad of the flip chip footprint to allow for high yield production and reliable flip chip joints. The volume and the consistency of eutectic solder on the PCB required for forming the flip chip joints between the flip chip and the PCB is greater than can be deposited using conventional methods, i.e., hot air solder leveling or controlled electrolytic plating. A method has been developed for depositing solder for the flip chip on a PCB which meets the above requirements. With this method fabricating a PCB comprises the conventional steps of drilling, depositing electroless copper, imaging, applying plating resist, plating, stripping plating resist, etching, and finally applying the solder mask, to form a pattern of metallization on a substrate. Subsequent, to these steps, a secondary process forms the solder deposits. The secondary process comprises the steps of applying plasma to the surface of the solder mask, to prepare the surface of the solder mask depositing a layer of copper over the solder mask to electrically couple the pattern of metallization on the substrate applying a layer of plating resist over the layer of copper at selected locations of the pattern of metallization depositing plating at the selected locations removing the plating resist stripping the deposited layer of copper reflowing the printed circuit causing the deposits at the selected locations to form solder bumps, and finally, flattening the solder bumps to form a level set of contact locations which align with the bond pads of an inverted semiconductor chip. A disadvantage of this method is, since the solder mask is applied before this secondary process is performed, the solder mask is exposed to each of these steps either directly or indirectly, thus, adversely affecting the quality and the reliability of the solder mask.
The plasma step roughens the surface of the solder mask which, although necessary to improve the adhesion of the layer of copper to the solder mask, degrades the solder mask making it susceptible to reliability problems. In addition, the plasma step is a difficult process to control to achieve a critical balance between a desired degree of roughness of the surface of the solder mask, and ensuring sufficient solder mask remains on the printed circuit. In addition, due to the cost of plasma, the plasma step is an expensive step. Further, in the copper removal step, the copper is stripped from the surface of the solder mask by etching. This step exposes the solder mask to the etching process and further contributes to weakening the solder mask.
Hence, it can be seen that a need exists for an economical and reliable method for fabricating printed circuits for semiconductor chips which does not degrade the solder mask and, preferably, does not require the use of plasma.